External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

10.7.2.1. Evaluating Hardware and Calibration Issues

Evaluate hardware and calibration issues using the Signal Tap II logic analyzer, as follows:
  • To evaluate hardware issues, monitor the local side read and write interface with the Signal Tap II logic analyzer, with the pass or fail or error signals as triggers
  • To evaluate calibration issues, monitor the various calibration signals with the Signal Tap II logic analyzer, with the pass or fail or error signals as triggers. Also use the EMIF debug toolkit and system consoles when available
  • For more information about the EMIF debug toolkit and the type of signals for debugging external memory interfaces, refer to the External Memory Interface Debug Toolkit chapter in volume 3 of the External Memory Interface Handbook.

Consider adding core noise to your design to aggravate margin timing and signal integrity issues. Steadily increasing the stress on the external memory interface is an ideal way to assess and understand the cause of any previously intermittent failures that you may observe in your system. Using the Signal Tap II probe tool can provide insights into the source or cause of operational failure in the system.

Steadily increasing stress on the external memory interface allows you to assess and understand the impact that such factors have on the amount of timing margin and resynchronization window. Take measurements with and without the additional stress factor to allow evaluation of the overall effect.

Steadily increase the stress on the interface in the following order:

  1. Increase the interface utilization by modifying the example driver to focus on the types of transactions that exhibit the issue. (For Arria 10 and Stratix 10 interfaces, you can implement an example design with the Traffic Generator 2.0 enabled, and then employ the EMIF Debug Toolkit to configure the data transaction and traffic pattern.)
  2. Increase the SSN or aggressiveness of the data pattern by modifying the example driver to output in synchronization PRBS data patterns, or hammer patterns.
  3. Increase the stress on the PDN by adding more and more core noise to your system. Try sweeping the fundamental frequency of the core noise to help identify resonances in your power system.

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