External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.5.1. DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices

The following table lists the FPGA pin utilization for DDR3 SDRAM with leveling interfaces.
Table 12.  DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices

Interface Pin Description

Memory Device Pin Name

FPGA Pin Utilization

Data

DQ

DQ in the pin table, marked as Q in the Quartus Prime Pin Planner. Each DQ group has a common background color for all of the DQ and DM pins, associated with DQS (and DQSn) pins. The ×4 DIMM has the following mapping between DQS and DQ pins:

  • DQS[0] maps to DQ[3:0]
  • DQS[9] maps to DQ[7:4]
  • DQS[1] maps to DQ[11:8]
  • DQS[10] maps to DQ[15:12]

The DQS pin index in other DIMM configurations typically increases sequentially with the DQ pin index (DQS[0]: DQ[3:0]; DQS[1]: DQ[7:4]; DQS[2]: DQ[11:8]). In this DIMM configuration, the DQS pins are indicted this way to ensure pin out is compatible with both ×4 and ×8 DIMMs.

Data Mask

DM

Data Strobe

DQS and DQSn

DQS and DQSn (S and Sbar in the Quartus Prime Pin Planner)

Address and Command

A[], BA[], CAS#, CKE, CS#, ODT, RAS#, WE#,

Any user I/O pin. To minimize skew, you should place address and command pins in the same bank or side of the device as the following pins: CK/CK# pins, DQ, DQS, or DM pins.

RESET#

Intel recommends that you use the 1.5V CMOS I/O standard on the RESET# signal. If your board is already using the SSTL‑15 I/O standard, you do not terminate the RESET# signal to VTT.

Memory system clock

CK and CK#

For controllers with UniPHY IP, you can assign the memory clock to any unused DIFF_OUT pins in the same bank or on the same side as the data pins. However, for Arria V GZ and Stratix V devices, place the memory clock pins to any unused DQ or DQS pins. Do not place the memory clock pins in the same DQ group as any other DQ or DQS pins.

If there are multiple CK/CK# pin pairs using Arria V GZ or Stratix V devices, you must place them on DIFFOUT in the same single DQ groups of adequate width. For example, DIMMs requiring three memory clock pin-pairs must use a ×4 DQS group.

Placing the multiple CK/CK# pin pairs on DIFFOUT in the same single DQ groups for Stratix III and Stratix IV devices improves timing.

Clock Source

Dedicated PLL clock input pin with direct (not using a global clock net) connection to the PLL and optional DLL required by the interface.

Reset

Dedicated clock input pin to accommodate the high fan-out signal.

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