External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.7. Timing Report DDR

The Report DDR task in the TimeQuest Timing Analyzer generates custom timing margin reports for all EMIF IP instances in your design. The TimeQuest Timing Analyzer generates this custom report by sourcing the wizard-generated <variation_name>_report_timing.tcl script.

This <variation_name>_report_timing.tcl script reports the following timing slacks on specific paths of the DDR SDRAM:

  • Read capture
  • Read resynchronization
  • Mimic, address and command
  • Core
  • Core reset and removal
  • Half-rate address and command
  • DQS versus CK
  • Write
  • Write leveling (tDQSS)
  • Write leveling (tDSS/tDSH)
  • DQS Gating (Postamble)

In Stratix III designs, the <variation_name>_report_timing.tcl script checks the design rules and assumptions as listed in “Timing Model Assumptions and Design Rules”. If you do not adhere to these assumptions and rules, you receive critical warnings when the TimeQuest Timing Analyzer runs during compilation or when you run the Report DDR task.

To generate a timing margin report, follow these steps:

  1. Compile your design in the Quartus Prime software.
  2. Launch the TimeQuest Timing Analyzer.
  3. Double-click Report DDR from the Tasks pane. This action automatically executes the Create Timing Netlist, Read SDC File, and Update Timing Netlist tasks for your project.
  • The .sdc may not be applied correctly if the variation top-level file is the top-level file of the project. You must have the top-level file of the project instantiate the variation top-level file.

The Report DDR feature creates a new DDR folder in the TimeQuest Timing Analyzer Report pane.

Expanding the DDR folder reveals the detailed timing information for each PHY timing path, in addition to an overall timing margin summary for the UniPHY instance, as shown in the following figure.

Figure 86. Timing Margin Summary Window Generated by Report DDR Task


Note: Bus turnaround time shown in the above figure is available in all UniPHY IPs and devices except in QDR II and QDR II+ SRAM memory protocols and Stratix III devices.

The following figure shows the timing analysis results calculated using FPGA timing model before adjustment in the Before Calibration panel.

Figure 87. Read and Write Before Calibration


The following two figures show the read capture and write margin summary window generated by the Report DDR Task for a DDR3 core. It first shows the timing results calculated using the FPGA timing model. The <variation_name>_report_timing_core.tcl then adjusts these numbers to account for effects that are not modeled by either the timing model or by TimeQuest Timing Analyzer. The read and write timing margin analysis for Stratix III devices does not need any adjustments.

Figure 88. Read Capture Margin Summary Window


Figure 89. Write Capture Margin Summary Window


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