External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

6.4. QDR II Layout Guidelines

The following table summarizes QDR II and QDR II SRAM general routing layout guidelines.
Note:
  1. The following layout guidelines include several +/- length based rules. These length based guidelines are for first order timing approximations if you cannot simulate the actual delay characteristics of your PCB implementation. They do not include any margin for crosstalk.
  2. Intel recommends that you get accurate time base skew numbers when you simulate your specific implementation.
  3. To reliably close timing to and from the periphery of the device, signals to and from the periphery should be registered before any further logic is connected.
Table 52.  QDR II and QDR II+ SRAM Layout Guidelines

Parameter

Guidelines

General Routing

  • If signals of the same net group must be routed on different layers with the same impedance characteristic, you must simulate your worst case PCB trace tolerances to ascertain actual propagation delay differences. Typical later to later trace delay variations are of 15 ps/inch order.
  • Avoid T-junctions greater than 150 ps.

Clock Routing

  • Route clocks on inner layers with outer-layer run lengths held to under 150 ps.
  • These signals should maintain a 10-mil (0.254 mm) spacing from other nets.
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Complementary clocks should maintain a length-matching between P and N signals of ±2 ps.
  • Keep the distance from the pin on the QDR II SRAM component to stub termination resistor (VTT) to less than 50 ps for the K, K# clocks.
  • Keep the distance from the pin on the QDR II SRAM component to fly-by termination resistor (VTT) to less than 100 ps for the K, K# clocks.
  • Keep the distance from the pin on the FPGA component to stub termination resistor (VTT) to less than 50 ps for the echo clocks, CQ, CQ#, if they require an external discrete termination.
  • Keep the distance from the pin on the FPGA component to fly-by termination resistor (VTT) to less than 100 ps for the echo clocks, CQ, CQ#, if they require an external discrete termination.

External Memory Routing Rules

  • Keep the distance from the pin on the QDR II SRAM component to stub termination resistor (VTT) to less than 50 ps for the write data, byte write select and address/command signal groups.
  • Keep the distance from the pin on the QDR II SRAM component to fly-by termination resistor (VTT) to less than 100 ps for the write data, byte write select and address/command signal groups.
  • Keep the distance from the pin on the FPGA (Arria II GX) to stub termination resistor (VTT) to less than 50 ps for the read data signal group.
  • Keep the distance from the pin on the FPGA (Arria II GX) to fly-by termination resistor (VTT) to less than 100 ps for the read data signal group.
  • Parallelism rules for the QDR II SRAM data/address/command groups are as follows:
    • 4 mils for parallel runs < 0.1 inch (approximately 1× spacing relative to plane distance).
    • 5 mils for parallel runs < 0.5 inch (approximately 1× spacing relative to plane distance).
    • 10 mils for parallel runs between 0.5 and 1.0 inches (approximately 2× spacing relative to plane distance).
    • 15 mils for parallel runs between 1.0 and 6.0 inch (approximately 3× spacing relative to plane distance).

Maximum Trace Length

  • Keep the maximum trace length of all signals from the FPGA to the QDR II SRAM components to 6 inches.

Did you find the information on this page useful?

Characters remaining:

Feedback Message