External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

1. Planning Pin and FPGA Resources

Updated for:
Intel® Quartus® Prime Design Suite 17.0

The External Memory Interface Handbook describes the UniPHY-based external memory interface IP available for use with Intel® V-series and earlier devices using UniPHY-based IP.

This chapter contains information for board designers who must determine FPGA pin usage, to create board layouts. The board design process sometimes occurs concurrently with the RTL design process.

Use this document with the External Memory Interfaces chapter of the relevant device family handbook.

Typically, all external memory interfaces require the following FPGA resources:

  • Interface pins
  • PLL and clock network
  • DLL
  • Other FPGA resources—for example, core fabric logic, and on-chip termination (OCT) calibration blocks

After you know the requirements for your external memory interface, you can start planning your system. The I/O pins and internal memory cannot be shared for other applications or external memory interfaces. However, if you do not have enough PLLs, DLLs, or clock networks for your application, you may share these resources among multiple external memory interfaces or modules in your system.

Ideally, any interface should reside entirely in a single bank; however, interfaces that span multiple adjacent banks or the entire side of a device are also fully supported. In addition, you may also have wraparound memory interfaces, where the design uses two adjacent sides of the device and the memory interface logic resides in a device quadrant. In some cases, top or bottom bank interfaces have higher supported clock rates than left or right or wraparound interfaces.