External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

9.12. Performing I/O Timing Analysis

For accurate I/O timing analysis, the Quartus Prime software must be made aware of the board trace and loading information. This information must be derived and refined during your PCB development process of pre-layout (line) and post‑layout (board) simulations.

For external memory interfaces that use memory modules (DIMMs), the board trace and loading information must include the trace and loading information of the module in addition to the main and host platform, which you can obtain from your memory vendor.

You can use the following I/O timing analysis methods for your memory interface:

  • Perform I/O Timing Analysis with 3rd Party Simulation Tools
  • Perform Advanced I/O Timing Analysis with Board Trace Delay Model