External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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7.3.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM for UniPHY IP

The following table lists the memory parameters for LPDDR2, DDR2 and DDR3 SDRAM.

Use the Memory Parameters tab to apply the memory parameters from your memory manufacturer’s data sheet.

Table 69.  Memory Parameters for LPDDR2, DDR2, and DDR3 SDRAM

Parameter

Description

Memory vendor

The vendor of the memory device. Select the memory vendor according to the memory vendor you use. For memory vendors that are not listed in the setting, select JEDEC with the nearest memory parameters and edit the parameter values according to the values of the memory vendor that you use. However, if you select a configuration from the list of memory presets, the default memory vendor for that preset setting is automatically selected.

Memory format

The format of the memory device.

Select Discrete if you are using just the memory device. Select Unbuffered or Registered for DIMM format. Use the DIMM format to turn on levelling circuitry for LPDDR2 support device only. DDR2 supports DIMM also.

Number of clock enables per device/DIMM

The number of clock enable pins per device or DIMM. This value also determines the number of ODT signals. (This parameter is available only when the selected memory format is Registered.)

Note: This parameter is not available for MAX 10 devices.

Number of chip selects per device/DIMM

The number of chip selects per device or DIMM. This value is not necessarily the same as the number of ranks for RDIMMs or LRDIMMs. This value must be 2 or greater for RDIMMs or LRDIMMs. (This parameter is available only when the selected memory format is Registered.)

Note: This parameter is not available for MAX 10 devices.

Number of ranks per slot

The number of ranks per DIMM slot. (This parameter is available only when the selected memory format is Registered.)

Note: This parameter is not available for MAX 10 devices.

Number of slots

The number of DIMM slots. (This parameter is available only when the selected memory format is Registered.)

Note: This parameter is not available for MAX 10 devices.

Memory device speed grade

The maximum frequency at which the memory device can run.

Total interface width

The total number of DQ pins of the memory device. Limited to 144 bits for DDR2 and DDR3 SDRAM (with or without leveling).

The total interface is depending on the rate on Avalon-MM interface because the maximum Avalon data width is 1024. If you select 144 bit for total interface width with Quarter-rate, the avalon data width is 1152 exceeding maximum avalon data width.

DQ/DQS group size

The number of DQ bits per DQS group.

Number of DQS groups

The number of DQS groups is calculated automatically from the Total interface width and the DQ/DQS group size parameters.

Number of chip selects (DDR2 and DDR3 SDRAM device only)

The number of chip-selects the IP core uses for the current device configuration.

Specify the total number of chip-selects according to the number of memory device.

Number of clocks

The width of the clock bus on the memory interface.

Row address width

The width of the row address on the memory interface.

Column address width

The width of the column address on the memory interface.

Bank-address width

The width of the bank address bus on the memory interface.

Enable DM pins

Specifies whether the DM pins of the memory device are driven by the FPGA. You can turn off this option to avoid overusing FPGA device pins when using x4 mode memory devices.

When you are using x4 mode memory devices, turn off this option for DDR3 SDRAM.

You must turn on this option if you are using Avalon byte enable.

DQS# Enable (DDR2)

Turn on differential DQS signaling to improve signal integrity and system performance.

This option is available for DDR2 SDRAM only.

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