External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.10.3.1. Read Data Assumptions for Stratix III Devices

For Stratix III devices the following additional read data and mimic pin assumptions are necessary:
  • For DDR3, DDR2, and DDR SDRAM interfaces, the read clock pin can only drive a DQS bus clocking a ×4 or ×9 DQ group.
  • For QDR II, QDR II+ SRAM, and RLDRAM II interfaces, the read clock pin can only drive a DQS bus clocking a ×9, ×18, or ×36 DQ group.
  • For non‑wraparound DDR, DDR2, and DDR3 interfaces, the mimic pin, all read clock, and all read data pins must be placed on the same edge of the device (top, bottom, left, or right). For wraparound interfaces, these pins can be placed on adjacent row I/O and column I/O edges and operate at reduced frequencies.
  • All read data pins and the mimic pin must feed DDIO_IN registers and their input delay chains D1, D2, and D3 set to default values.
  • DQS phase‑shift setting must be either 72° or 90° (supports only one phase shift for each operating band and memory standard).
  • All read clock pins must have the dqs_ctrl_latches_enable parameter of its DQS_DELAY_CHAIN WYSIWYG set to false.
  • The read clocks pins must have their D4 delay chain set to the Quartus Prime software default value of 0.
  • The read data pins must have their T8 delay chain set to the Quartus Prime software default value of 0.
  • When differential DQS strobes are used (DDR3 and DDR2 SDRAM), the mimic pin must feed a true differential input buffer. Placing the memory clock pin on a DIFFIO_RX pin pair allows the mimic path to track timing variations on the DQS input path.
  • When single ended DQS strobes are used, the mimic pin must feed a single ended input buffer.

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