External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.1. Interface Pins

Any I/O banks that do not support transceiver operations in Arria® II, Arria V, Arria 10, Stratix® III, Stratix IV, and Stratix V devices support external memory interfaces. However, DQS (data strobe or data clock) and DQ (data) pins are listed in the device pin tables and fixed at specific locations in the device. You must adhere to these pin locations as these locations are optimized in routing to minimize skew and maximize margin. Always check the external memory interfaces chapters from the device handbooks for the number of DQS and DQ groups supported in a particular device and the pin table for the actual locations of the DQS and DQ pins.

The following table lists a summary of the number of pins required for various example memory interfaces. This table uses series OCT with calibration and parallel OCT with calibration, or dynamic calibrated OCT, when applicable, shown by the usage of RUP and RDN pins or RZQ pin.

Table 1.  Pin Counts for Various Example External Memory Interfaces (1) (2)

External Memory Interface

FPGA DQS Group Size

Number of DQ Pins

Number of DQS/CQ/QK Pins

Number of Control Pins

(19)

Number of Address Pins  (3)

Number of Command Pins

Number of Clock Pins

RUP/RDN

Pins  (4)

RZQ Pins  (11)

Total Pins (with RUP/RDN pins)

Total Pins (with RZQ pin)

LPDDR2

×8

8

2

1

10

2

2

N/A

1

N/A

26

16

4

2

10

2

2

N/A

1

N/A

37

72

18

9

10

2

2

N/A

1

N/A

114

LPDDR3 ×8

16

4

2

10

2

2

N/A

1

N/A

37

72

18

9

10

2

2

N/A

1

N/A

114

DDR4 SDRAM (12)

x4 4 2 0 (7) 17 11 2

N/A

1

N/A

37
x8 8 2 1 17 11 2

N/A

1

N/A

42
16 4 2 17 10 (13) 2

N/A

1

N/A

52

DDR3 SDRAM  (5)  (6)

×4

4

2

0  (7)

14

10

2

2

1

34

33

×8

8

2

1

14

10

2

2

1

39

38

16

4

2

14

10

2

2

1

50

49

DDR2 SDRAM  (8)

×4

4

1

1  (7)

15

9

2

2

1

34

33

×8

8

1  (9)

1

15

9

2

2

1

38

37

16

2  (9)

2

15

9

2

2

1

48

47

DDR SDRAM  (6)

×4

4

1

1  (7)

14

7

2

2

1

29

28

×8

8

1

1

14

7

2

2

1

33

35

16

2

2

14

7

2

2

1

43

42

QDR II+ / II+ Xtreme SRAM  (18)

×18

36

2

2

19

3  (10)

2 (15)

2

1

66

65

×36

72

2

4

18

3  (10)

2 (15)

2

1

103

102

QDR II SRAM

×9

18

2

1

19

2

4 (16)

2

1

48

47

×18

36

2

2

18

2

4 (16)

2

1

66

65

×36

72

2

4

17

2

4 (16)

2

1

103

102

QDR IV SRAM (20)

x18

36

8

5

22

7

10 (17)

N/A

1

N/A

89

x36

72

8

5

21

7

10 (17)

N/A

1

N/A

124

RLDRAM 3 CIO (14)

x9 18 4 2 20 8 (10)

6 (17)

N/A

1

N/A

59
36 8 2 19 8 (10)

6 (17)

N/A

1

N/A

80

RLDRAM
II CIO

×9

9

2

1

22

7  (10)

4 (17)

2

1

47

46

18

4

1

21

7  (10)

4 (17)

2

1

57

56

×18

36

4

1

20

7  (10)

6 (17)

2

1

76

75

Notes to table:

  1. These example pin counts are derived from memory vendor data sheets. Check the exact number of addresses and command pins of the memory devices in the configuration that you are using.
  2. PLL and DLL input reference clock pins are not counted in this calculation.
  3. The number of address pins depends on the memory device density.
  4. Some DQS or DQ pins are dual purpose and can also be required as RUP , RDN , or configuration pins. A DQS group is lost if you use these pins for configuration or as RUP or RDN pins for calibrated OCT. Pick RUP and RDN pins in a DQS group that is not used for memory interface purposes. You may need to place the DQS and DQ pins manually if you place the RUP and RDN pins in the same DQS group pins.
  5. The TDQS and TDQS# pins are not counted in this calculation, as these pins are not used in the memory controller.
  6. Numbers are based on 1-GB memory devices.
  7. Intel® FPGAs do not support DM pins in ×4 mode with differential DQS signaling.
  8. Numbers are based on 2-GB memory devices without using differential DQS, RDQS, and RDQS# pin support.
  9. Assumes single ended DQS mode. DDR2 SDRAM also supports differential DQS, which makes these DQS and DM numbers identical to DDR3 SDRAM.
  10. The QVLD pin that indicates read data valid from the QDR II+ SRAM or RLDRAM II device, is included in this number.
  11. RZQ pins are supported by Arria V, Arria 10, Cyclone V, and Stratix V devices.
  12. Numbers are based on 2-GB discrete device with alert flag and address and command parity pins included.
  13. DDR4 x16 devices support only a bank group of 1.
  14. Numbers are based on a 576-MB device.
  15. These numbers include K and K# clock pins. The CQ and CQ# clock pins are calculated in a separate column.
  16. These numbers include K, K#, C, and C# clock pins. The CQ and CQ# clock pins are calculated in a separate column.
  17. These numbers include CK, CK#, DK, and DK# clock pins. QK and QK# clock pins are calculated in a separate column.
  18. This number is based on a 36864-kilobit device.
  19. For DDR,DDR2,DDR3,LPDDR2, LPDDR3 SDRAM, RLDRAM 3, RLDRAM II, they are DM pins. For QDR II/II+/Extreme, they are BWS pins. For DDR4, they are DM/DBI pins. For QDR IV, they are DINVA[1:0], DINVB[1:0], and AINV.

  20. This number is based on a 144-Mbit device with address bus inversion and data bus inversion bits included.
Note: Maximum interface width varies from device to device depending on the number of I/O pins and DQS or DQ groups available. Achievable interface width also depends on the number of address and command pins that the design requires. To ensure adequate PLL, clock, and device routing resources are available, you should always test fit any IP in the Quartus® Prime software before PCB sign-off.

Intel® devices do not limit the width of external memory interfaces beyond the following requirements:

  • Maximum possible interface width in any particular device is limited by the number of DQS groups available.
  • Sufficient clock networks are available to the interface PLL as required by the IP.
  • Sufficient spare pins exist within the chosen bank or side of the device to include all other address and command, and clock pin placement requirements.
  • The greater the number of banks, the greater the skew, hence Intel® recommends that you always generate a test project of your desired configuration and confirm that it meets timing.

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