External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

13. Power Estimation Methods for External Memory Interfaces

The following table lists the supported power estimation methods for external memory interfaces.
Table 505.  Power Estimation Methods for External Memory Interfaces

Method

Vector Source

UniPHY Support

Accuracy

Estimation Time  (1)

Early power estimator (EPE)

Not applicable

v

Lowest



Highest

Fastest



Slowest

Vector-less power analysis (PPPA)

Not applicable

v

Vector-based power analysis

RTL simulation

v

Zero-delay simulation  (2)

v

Timing simulation

 (2)

Notes to Table:

  1. To decrease the estimation time, you can skip power estimation during calibration. Power consumption during calibration is typically equivalent to power consumption during user mode.
  2. Power analysis using timing simulation vectors is not supported.

When using Intel® FPGA IP, you can use the zero-delay simulation method to analyze the power required for the external memory interface. Zero-delay simulation is as accurate as timing simulation for 95% designs (designs with no glitching). For a design with glitching, power may be under estimated.

For more information about zero-delay simulation, refer to the Power Estimation and Analysis section in the Quartus ® Prime Handbook.

Note: The size of the vector file (. vcd) generated by zero-delay simulation of an DDR3 SDRAM High-Performance Controller example design is 400 GB. The . vcd includes calibration and user mode activities. When vector generation of calibration phase is skipped, the vector size decreases to 1 GB.

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