External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents Additional Guidelines for MAX 10 Devices

The following additional guidelines apply when you implement an external memory interface for a MAX 10 device.

I/O Pins Not Available for DDR3 or LPDDR2 External Memory Interfaces (Preliminary)

The I/O pins named in the following table are not available for use when implementing a DDR3 or LPDDR2 external memory interface for a MAX 10 device.

F256 U324 F484 F672
10M16 N16 R15 U21
P16 P15 U22
R18 M21
P18 L22
E16 E19
D16 F18
10M25 N16 U21
P16 U22
10M50 W23
N16 U21 T24
P16 U22 R25
M21 R24
L22 P25
F21 K23
F20 K24
E19 J23
F18 H23
F17 G23
E17 F23

Additional Restrictions on I/O Pin Availability

The following restrictions are in addition to those represented in the above table.

  • When implementing a DDR3 or LPDDR2 external memory interface, you can use only 75 percent of the remaining I/O pins in banks 5 and 6 for normal I/O operations.
  • When implementing a DDR2 external memory interface, 25 percent of the remaining I/O pins in banks 5 and 6 can be assigned only as input pins.

MAX 10 Board Design Considerations

  • For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
  • To minimize unwanted inductance from the board via, Intel recommends that you keep the PCB via depth for VCCIO banks below 49.5 mil.
  • For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Intel recommends that you use termination resistor value of 80 Ω to VTT.
  • For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for DDR3, or less than three inches for LPDDR2.

Power Supply Variation for LPDDR2 Interfaces

For an LPDDR2 interface that targets 200 MHz, constrain the memory device I/O and core power supply variation to within ±3%.

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