External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.2.1. Arria II Device PHY Timing Paths

The following table lists all Arria II devices external memory interface timing paths.
Table 495.  Arria II Devices External Memory Interface Timing Paths   (1)    

Timing Path

Circuit Category

Source

Destination

Read Data  (2)  (6)

Source-Synchronous

Memory DQ, DQS Pins

DQ Capture Registers in IOE

Write Data  (2)  (6)

Source-Synchronous

FPGA DQ, DQS Pins

Memory DQ, DM, and DQS Pins

Address and command  (2)

Source-Synchronous

FPGA CK/CK# and Addr/Cmd Pins

Memory Input Pins

Clock-to-Strobe  (2)

Source-Synchronous

FPGA CK/CK# and DQS Output Pins

Memory Input Pins

Read Resynchronization  (2)

Calibrated

IOE Capture Registers

IOE Resynchronization Registers

Read Resynchronization  (2)  (5)

Calibrated

IOE Capture Registers

Read FIFO in FPGA Core

PHY IOE-Core Paths  (2)

Source-Synchronous

IOE Resynchronization Registers

FIFO in FPGA Core

PHY and Controller Internal Paths  (2)

Internal Clock fMAX

Core Registers

Core Registers

I/O Toggle Rate  (3)

I/O

FPGA Output Pin

Memory Input Pins

Output Clock Specifications (Jitter, DCD)  (4)

I/O

FPGA Output Pin

Memory Input Pins

Notes to Table:

  1. Timing paths applicable for an interface between Arria II devices and SDRAM component.
  2. Timing margins for this path are reported by the TimeQuest Timing Analyzer Report DDR function.
  3. Intel recommends that you perform signal integrity simulations to verify I/O toggle rate.
  4. For output clock specifications, refer to the Arria II Device Data Sheet chapter of the Arria II Handbook.
  5. Only for UniPHY IP.
  6. Arria II GX devices use source-synchronous and calibrated path.

The following figure shows the Arria II GX devices input datapath registers and circuit types.

Note: UniPHY IP interfaces bypass the synchronization registers.
Figure 67. Arria II GX Devices Input Data Path Registers and Circuit Types in SDRAM Interface


The following figure shows the Arria II GZ devices input datapath registers and circuit types.

Figure 68. Arria II GZ Devices Input Data Path Registers and Circuit Types in SDRAM Interface


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