External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback DQS versus CK—Arria II GX and Cyclone IV Devices

The DQS versus CK timing path indicates the skew requirement for the arrival time of the DQS strobe at the memory with respect to the arrival time of CK/CK# at the memory. Arria II GX and Cyclone IV devices require the DQS strobes and CK clocks to arrive edge aligned.

There are two timing constraints for DQS versus CK timing path to account for duty cycle distortion. The DQS/DQS# rising edge to CK/CK# rising edge (tDQSS) requires the rising edge of DQS to align with the rising edge of CK to within 25% of a clock cycle, while the DQS/DQS# falling edge setup/hold time from CK/CK# rising edge (tDSS/tDSH) requires the falling edge of DQS to be more than 20% of a clock cycle away from the rising edge of CK.

The Timing Analyzer analyzes the DQS vs CK timing paths using the set_output_delay (max and min) constraints. For more information, refer to <phy_variation_name> _phy_ddr_timing.sdc.