External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

7.2.4. Board Settings

Use the Board Settings tab to model the board-level effects in the timing analysis.

The Board Settings tab allows you to specify the following settings:

  • Setup and hold derating (For DDR2, DDR3, and LPDDR3 external memory interfaces, and RLDRAM 3 and RLDRAM II external memory interfaces)
  • Channel Signal Integrity
  • Board skews
Note: For accurate timing results, you must enter board settings parameters that are correct for your PCB.

The IP core supports single and multiple chip-select configurations. Intel has determined the effects on the output signaling of single-rank configurations for certain Intel® boards, and included the channel uncertainties in the Quartus Prime timing models.

Because the Quartus Prime timing models hold channel uncertainties that are representative of specific Intel boards, you must determine the board-level effects of your board, including any additional channel uncertainty relative to Intel's reference design, and enter those values into the Board Settings panel in the parameter editor. You can use HyperLynx or a similar simulator to obtain values that are representative of your board.

For more information about how to include your board simulation results in the Quartus Prime software, refer to the following sections. For more information about how to assign pins using pin planners, refer to the design flow tutorials and design examples on the List of Designs Using Intel External Memory IP page of the Intel® FPGA Wiki page.

For more general information about timing deration methodology, refer to the Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs section in the Analyzing Timing of Memory IP chapter.