External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

8.2.8.1. Running Post-fit Simulation

Assuming that the UniPHY IP has been generated and inserted in some larger design, follow these steps to run post-fit simulation:
  1. In the Quartus Prime software, set up a project that contains a UniPHY IP core.
  2. On the Assignments menu, click Assignment Editor.
  3. In the assignment editor, add the global assignment VERILOG_MACRO and set the value to SYNTH_FOR_SIM=1.
  4. On the Assignments menu, click Settings.
  5. In the Category list, under EDA Tools Settings, select Simulation.
  6. On the Simulation page, select a tool name (for example, ModelSim* - Intel FPGA Edition).
  7. In the Format for output netlist list, select a HDL language.
  8. In the Output directory box, type or browse to the location where you want output files saved.
  9. Click More EDA Netlist Writer Settings to choose from a list of other options.
  10. Set the value for Maintain hierarchy to PARTITION_ONLY, and click OK.
  11. Elaborate the project. On the Processing menu, select Start and click Start Hierarchy Elaboration.
  12. In the Project Navigator window, click the Hierarchy tab. In the Entity box, locate the instances for the following devices:
    1. For instances in Stratix III, Stratix IV, Arria II GX, Arria II GZ , click the + icon to expand the following top-level design entities, right-click on the lower-level entities, select Design Partition, and click Set as Design Partition:
      • <hierarchy path to UniPHY top-level>\<name>_if0:if0\<name>_if0_p0:p0
      • <hierarchy path to UniPHY top-level>\<name>_if0:if0\<name>_if0_s0:s0
    2. For instances in Arria V or Stratix V, click the + icon to expand the following top-level design entity, right-click on the lower-level entities, select Design Partition, and click Set as Design Partition:
      • <hierarchy path to UniPHY top-level>\<name>_if0:if0\<name>_if0_s0:s0

      For instances of hard memory interfaces in Arria V, no design partition is necessary.

  13. In the Design Partitions Window, ensure that the netlist type value of the design partitions listed in Step12 a and 12b are set to Post-synthesis.
  14. On the Processing menu, select Start and click Start Analysis and Synthesis.
  15. Run the Pin assignments script. To run the pin assignment script, follow these steps:
    1. On the Tools menu,click TCL Scripts.
    2. In the Libraries list, locate the <name>_pin_assignment.tcl.
    3. Click Run.
  16. On the Processing menu, select Start and click Partition Merge.
  17. On the Processing menu, select Start and click Start Fitter.
  18. On the Processing menu, select Start and click Start EDA netlist writer .
  19. The output post-fit netlist is located in the directory you chose in Step 8.
  20. Assume that the netlist filename is dut.vo (or dut.vho for VHDL). Replace the instance of the partitioned modules (specified in step 12) in dut.vo and instantiate the original instance of the RTL. As a result, the RTL of those modules will simulate correctly instead of the the post-fit netlist. For example, you can delete the definition of the <name>_if0_s0 (and <name>_if0_p0, if appropriate) modules in the post-fit netlist, and ensure that your simulator compiles the post-fit netlist and all the UniPHY RTL in order to properly link these modules for simulation.

    (This step does not apply to hard memory interfaces on Arria V devices.)

  21. To match the post-fit netlist instantiation of s0 (and p0, if appropriate) with the original RTL module definition (specified in step 12), you must also account for three device input ports that are added to the post-fit netlist. The easiest way to do this is to delete the following three connections from the s0 (and p0, if appropriate) instances in the post-fit netlist:
    • .devpor(devpor)
    • .devclrn(devclrn)(
    • .devoe(devpoe)

    (This step does not apply to hard memory interfaces on Arria V devices.)

  22. For Stratix V the <name>_if0_s0 instance in the post-fit netlist will also have a connection .QIC_GND_ PORT( <wire name> ) that you must delete because it does not match with the original RTL module.

    (This step does not apply to hard memory interfaces on Arria V devices.)

  23. Set up and run your simulator.

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