External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.10.1. Memory Clock Output Assumptions

To verify the quality of the FPGA clock output to the memory device (CK/CK# or K/K#), which affects FPGA performance and quality of the read clock/strobe used to read data from the memory device, the following assumptions are necessary:
  • The slew rate setting must be Fast or an on‑chip termination (OCT) setting must be used.
  • The output delay chains must all be 0 (the default value applied by the Quartus Prime software). These delay chains include the Stratix III D5 and D6 output delay chains.
  • The output open‑drain parameter on the memory clock pin IO_OBUF atom must be Off. The Output Open Drain logic option must not be enabled.
  • The weak pull-up on the CK and CK# pads must be Off. The Weak Pull Up Resistor logic option must not be enabled.
  • The bus hold on the CK and CK# pads must be Off. The Enable Bus Hold Circuitry logic option must not be enabled.
  • All CK and CK# pins must be declared as output‑only pins or bidirectional pins with the output enable set to VCC.

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