External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

9.1.1. Source-Synchronous Paths

Source-synchronous timing paths are those where clock and data signals pass from the transmitting device to the receiving device.

An example of a source-synchronous timing path is the FPGA-to-memory write datapath. The FPGA device transmits DQ output data signals to the memory along with a center-aligned DQS output strobe signal. The memory device uses the DQS signal to clock the data on the DQ pins into its internal registers.

Note: For brevity, the following topics refer to data signals and clock strobe signals as DQ signals and DQS signals, respectively. While the terminology is formally correct only for DDR-type interfaces and does not match QDR II, QDR II+ and RLDRAM II pin names, the behavior is similar enough that most timing properties and concepts apply to both. The clock that captures address and command signals is always referred to as CK/CK# too.

Did you find the information on this page useful?

Characters remaining:

Feedback Message