External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.6.3. Number of Clock Networks Available in Intel® Device Families

The following table lists the number of clock networks available in Intel® device families.
Table 20.  Number of Clock Networks Available in Intel® Device Families (1)

Device Family

Global Clock Network

Regional Clock Network

Arria II GX

16

48

Arria II GZ

16

64–88

Arria V

16

88

Arria V GZ

16

92

Cyclone V

16

N/A

MAX 10 FPGA

10

Stratix III

16

64–88

Stratix IV

16

64–88

Stratix V

16

92

Note to Table:

  1. For more information on the number of available clock network resources per device quadrant to better understand the number of clock networks available for your interface, refer to the Clock Networks and PLL chapter of the respective device family handbook.
Note: You must decide whether you need to share clock networks, PLL clock outputs, or PLLs if you are implementing multiple memory interfaces.

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