External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Public
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10. Debugging Memory IP

The following topics describe the tools and processes for debugging external memory interfaces.

The discussion focuses on issues pertaining to the Intel® DDR, DDR2, DDR3, LPDDR2, QDRII, QDRII+, RLDRAM II, and RLDRAM 3 IP.

In general, memory debugging issues can be categorized as follows:

  • Resource and planning issues
  • Interface configuration issues
  • Functional issues
  • Timing issues

Some issues may not be directly related to interface operation; problems can also occur at the Intel® Quartus® Prime Fitter stage, or in timing analysis.