External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

10. Debugging Memory IP

The following topics describe the tools and processes for debugging external memory interfaces.

The discussion focuses on issues pertaining to the Intel® DDR, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, QDRII, QDRII+, QDRII+ Xtreme, QDR-IV, RLDRAM II, and RLDRAM 3 IP.

In general, memory debugging issues can be categorized as follows:

  • Resource and planning issues
  • Interface configuration issues
  • Functional issues
  • Timing issues

Some issues may not be directly related to interface operation; problems can also occur at the Quartus® Prime Fitter stage, or in timing analysis.

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