External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

8.2.3. Functional Simulation with Verilog HDL

Simulation scripts for the Synopsys, Cadence, Aldec, and Mentor Graphics simulators are provided for you to run the example design.

The simulation scripts are located in the following main folder locations:

Simulation scripts in the simulation folders are located as follows:

  • <variation_name>_example_design\simulation\verilog\mentor\msim_setup.tcl
  • <variation_name>_example_design\simulation\verilog\synopsys\vcs\vcs_setup.sh
  • <variation_name>_example_design\simulation\verilog\synopsys\vcsmx\vcsmx_setup.sh
  • <variation_name>_example_design\simulation\verilog\aldec\rivierapro_setup.tcl
  • <variation_name>_example_design\simulation\verilog\cadence\ncsim_setup.sh

Simulation scripts in the <>_sim_folder are located as follows:

  • <variation_name>_sim\mentor\msim_setup.tcl
  • <variation_name>_sim\cadence\ncsim_setup.sh
  • <variation_name>_sim\synopsys\vcs\vcs_setup.sh
  • <variation_name>_sim\vcsmx\vcsmx_setup.sh
  • <variation_name>_sim\aldec\rivierapro_setup.tcl

For more information about simulating Verilog HDL or VHDL designs using command lines, refer to the Mentor Graphics ModelSim* and QuestaSim Support chapter in volume 3 of the Quartus Prime Handbook.