External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

4.1.2.3. Termination Schemes

The following table lists the recommended termination schemes for major LPDDR2 SDRAM memory interface signals.

These signals include data (DQ), data strobe (DQS), data mask (DM), clocks (CK, and CK#), command address (CA), and control (CS#, and CKE).

Table 39.  Termination Recommendations for Arria V and Cyclone V Devices

Signal Type

HSUL-12 Standard  (1)  (2)

Memory End Termination

DQS/DQS#

R34 CAL

ZQ40

Data (Write)

R34 CAL

Data (Read)

ZQ40

Data Mask (DM)

R34 CAL

CK/CK# Clocks

R34 CAL

×1 = – (4)

×2 = 200 -ohmDifferential  (5)

Command Address (CA),

R34 CAL

Chip Select (CS#)

R34 CAL

Clock Enable (CKE)  (3)

R34 CAL

4.7 K-ohmparallel to GND

Notes to Table:

  1. R is effective series output impedance.
  2. CAL is OCT with calibration.
  3. Intel recommends that you use a 4.7 K-ohmparallel to GND if your design meets the power sequencing requirements of the LPDDR2 SDRAM component. Refer to the LPDDR2 SDRAM data sheet for further information.
  4. ×1 is a single-device load.
  5. ×2 is a double-device load. An alternative option is to use a 100 -ohm differential termination at the trace split.
Note: The recommended termination schemes in the above table are based on 2.8 inch maximum trace length analysis. You may add the external termination resistor or adjust the drive strength to improve signal integrity for longer trace lengths. Recommendations for external termination are as follows:
  • Class I termination (50 ohms parallel to VTT at the memory end) — Unidirectional signal (Command Address, control, and CK/CK# signals)
  • Class II termination (50 ohms parallel to VTT at both ends) — Bidirectional signal ( DQ and DQS/DQS# signal)

Intel recommends that you simulate your design to ensure good signal integrity.

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