External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

9.9. Common Timing Closure Issues

The following topics describe potential timing closure issues that can occur when using the UniPHY IP.

For possible timing closure issues with UniPHY variations, refer to the Quartus Prime Software Release Notes for the software version that you are using. You can solve some timing issues by moving registers or changing the project fitting setting to Standard (from Auto).

The Quartus Prime Software Release Notes list common timing issues that can be encountered in a particular version of the Quartus Prime software.

Note: In UniPHY-based memory controllers, the derive_pll_clocks command can affect timing closure if it is called before the memory controller files are loaded. Ensure that the Quartus Prime IP File (.qip) appears in the file list before any Synopsys Design Constraint Files (.sdc) files that contain derive_pll_clocks.