External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents Constraining the Design

For Arria 10 External Memory Interface IP for HPS, pin location assignments are predefined in the Quartus Prime IP file (.qip). In UniPHY-based and non-HPS Arria 10 external memory interfaces, you must make your own location assignments.
Note: You should not overconstrain any EMIF IP-related registers unless you are advised to do so by Intel, or you fully understand the effect on the external memory interface operation. Also, ensure that any wildcards in your user logic do not accidentally target EMIF IP-related registers.

For more information about timing constraints and analysis, refer to Analyzing Timing of Memory IP.

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