External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.8. Timing Model Assumptions and Design Rules

External memory interfaces using Intel FPGA IP are optimized for highest performance, and use a high‑performance timing model to analyze calibrated and source‑synchronous, double‑data rate I/O timing paths. This timing model applies to designs that adhere to a set of predefined assumptions.

These timing model assumptions include memory interface pin‑placement requirements, PLL and clock network usage, I/O assignments (including I/O standard, termination, and slew rate), and many others.

For example, the read and write datapath timing analysis is based on the FPGA pin‑level tTCCS and tSW specifications, respectively. While calculating the read and write timing margins, the Quartus Prime software analyzes the design to ensure that all read and write timing model assumptions are valid for your variation instance.

Note: Timing model assumptions only apply to Stratix III devices.

When the Report DDR task or report_timing.tcl script is executed, the timing analysis assumptions checker is invoked with specific variation configuration information. If a particular design rule is not met, the Quartus Prime software reports the failing assumption as a Critical Warning message.

The following figure shows a sample set of messages generated when the memory interface DQ, DQS, and CK/CK# pins are not placed in the same edge of the device.

Figure 71. Read and Write Timing Analysis Assumption Verification