External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.10.1.1. Memory Clock Assumptions for Stratix III Devices

For Stratix III devices the following additional memory clock assumptions are necessary:
  • All memory clock output pins must be placed on DIFFOUT pin pairs on the same edge of the device.
  • For DDR3 SDRAM interfaces:
  • The CK pins must be placed on FPGA output pins marked DQ, DQS, or DQSn.
  • The CK pin must be fed by an OUTPUT_PHASE_ALIGNMENT WYSIWYG with a 0° phase shift.
  • The PLL clock driving CK pins must be the same as the clock driving the DQS pins.
  • The T4 (DDIO_MUX) delay chains setting for the memory clock pins must be the same as the settings for the DQS pins.
  • For non-DDR3 interfaces, the T4 (DDIO_MUX) delay chains setting for the memory clock pins must be greater than 0.
  • The programmable rise and fall delay chain settings for all memory clock pins must be set to 0.
  • The memory output clock signals must be generated with the DDIO configuration shown in the following figure, with a signal splitter to generate the n- pin pair and a regional clock network‑to‑clock to output DDIO block.
Figure 92. DDIO Configuration with Signal Splitter


Did you find the information on this page useful?

Characters remaining:

Feedback Message