External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.2.1.4.1. Adding Pins and DQ Group Assignments

The assignments defined in the <variation_name>_pin_assignments.tcl script (for UniPHY-based IP) and the Quartus Prime IP file (.qip) (for Arria 10 EMIF IP) help you to set up the I/O standards and the input/output termination for the external memory interface IP. These assignments also help to relate the DQ pin groups together for the Quartus Prime Fitter to place them correctly.
  • For UniPHY-based external memory interfaces, run the <variation_name>_pin_assignments.tcl script to apply the input and output termination, I/O standards, and DQ group assignments to your design. To run the pin assignment script, follow these steps:
    1. On the Processing menu, point to Start, and click Start Analysis and Synthesis. Allow Analysis and Synthesis to finish without errors before proceeding to step 2.
    2. On the Tools menu click Tcl Scripts.
    3. Specify the pin_assignments.tcl and click Run.
    The pin assignment script does not create a PLL reference clock for the design. You must create a clock for the design and provide pin assignments for the signals of both the example driver and testbench that the IP core variation generates.
    Note: For some UniPHY-based IP configurations, the afi_clk clock does not have a global signal assignment constraint. In this case, you should add a suitable assignment for your design. For example, for a UniPHY-based DDR3 IP targeting a Stratix IV device, if0|pll0|upll_memphy|auto_generated|clk[0] does not have a global signal assignment and you should consider adding either a global clock or a dual regional clock assignment to your project for this clock.
  • For Arria 10 External Memory Interface IP, the Quartus Prime software automatically reads assignments from the .qip file during compilation, so it is not necessary to apply assignments to your design manually.
Note:
  • If you must overwrite the default assignments, ensure that you make your changes in the Quartus Prime Settings File (.qsf) and not the .qip file. Assignments in the .qsf file take precedence over assignments in the .qip file. Note also, that if you rerun the <variation_name>_pin_assignments.tcl file, it overwrites your changes.
  • If the PLL input reference clock pin does not have the same I/O standard as the memory interface I/Os, a no-fit might occur because incompatible I/O standards cannot be placed in the same I/O bank.
  • If you are upgrading your memory IP from an earlier Quartus Prime version, rerun the pin_assignments.tcl script in the later Quartus Prime revision.
  • If you encounter a shortage of clock resources, the AFI clock domain can be moved between regional, dual-regional, and global. Moving any other clock domain can result in fit errors or timing closure problems.

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