External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents Interfacing with ×9 RLDRAM II CIO Devices

RLDRAM 3 devices do not have the x9 configuration.

RLDRAM II devices have the following pins:

  • 2 pins for QK and QK# signals
  • 9 DQ pins (in a ×8/×9 DQS group)
  • 2 pins for DK and DK# signals
  • 1 DM pin
  • 14 pins total (15 if you have a QVLD)

In the FPGA, the ×8/×9 DQS group consists of 12 pins: 2 for the read clocks and 10 for the data. In this case, move the QVLD (if you want to keep this connected even though this is not used in the Intel® FPGA memory interface solution) and the DK and DK# pins to the adjacent DQS group. If that group is in use, move to any available user I/O pins in the same I/O bank.

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