External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

4.1. LPDDR2 Guidance

The LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP enables you to implement LPDDR2 SDRAM interfaces with Arria® V and Cyclone® V devices.

The following topics focus on key factors that affect signal integrity:

  • I/O standards
  • LPDDR2 configurations
  • Signal terminations
  • Printed circuit board (PCB) layout guidelines

I/O Standards

LPDDR2 SDRAM interface signals use HSUL-12 JEDEC I/O signaling standards, which provide low power and low emissions. The HSUL-12 JEDEC I/O standard is mainly for point-to-point unterminated bus topology. This standard eliminates the need for external series or parallel termination resistors in LPDDR2 SDRAM implementation. With this standard, termination power is greatly reduced and programmable drive strength is used to match the impedance.

To select the most appropriate standard for your interface, refer to the the Device Datasheet for Arria V Devices chapter in the Arria V Device Handbook, or the Device Datasheet for Cyclone V Devices chapter in the Cyclone V Device Handbook.