External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

2.1.3. Dynamic On-Chip Termination

Dynamic OCT is available in Arria V, Arria 10, Cyclone V, Stratix III, Stratix IV, Stratix V, and Stratix 10.

The dynamic OCT scheme enables series termination (RS) and parallel termination (RT) to be dynamically turned on and off during the data transfer. The series and parallel terminations are turned on or off depending on the read and write cycle of the interface. During the write cycle, the RS is turned on and the RT is turned off to match the line impedance. During the read cycle, the RS is turned off and the RT is turned on as the FPGA implements the far-end termination of the bus.

For more information about dynamic OCT, refer to the I/O features chapters in the devices handbook for your Intel® device.

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