External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

1.4.1. General Pin-out Guidelines for UniPHY-based External Memory Interface IP

For best results in laying out your UniPHY-based external memory interface, you should observe the following guidelines.
Note: For a unidirectional data bus as in QDR II and QDR II+ SRAM interfaces, do not split a read data pin group or a write data pin group onto two sides. You should also not split the address and command group onto two sides either, especially when you are interfacing with QDR II and QDR II+ SRAM burst‑length‑of‑two devices, where the address signals are double data rate. Failure to adhere to these rules might result in timing failure.

In addition, there are some exceptions for the following interfaces:

  • ×36 emulated QDR II and QDR II+ SRAM in Arria II, Stratix III, and Stratix IV devices.
  • RLDRAM II and RLDRAM 3 CIO devices.
  • QDR II/+ SDRAM burst-length-of-two devices.
  • You must compile the design in the Quartus Prime software to ensure that you are not violating signal integrity and Quartus Prime placement rules, which is critical when you have transceivers in the same design.

The following are general guidelines for placing pins optimally for your memory interfaces:

  1. For Arria II GZ, Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V designs, if you are using OCT, the RUP and RDN, or RZQ pins must be in any bank with the same I/O voltage as your memory interface signals and often use two DQS or DQ pins from a group. If you decide to place the RUP and RDN, or RZQ pins in a bank where the DQS and DQ groups are used, place these pins first and then determine how many DQ pins you have left, to find out if your data pins can fit in the remaining pins. Refer to OCT Support for Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices.
  2. Use the PLL that is on the same side of the memory interface. If the interface is spread out on two adjacent sides, you may use the PLL that is located on either adjacent side. You must use the dedicated input clock pin to that particular PLL as the reference clock for the PLL. The input of the memory interface PLL cannot come from the FPGA clock network.
  3. The Intel® FPGA IP uses the output of the memory interface PLL as the DLL input reference clock. Therefore, ensure you select a PLL that can directly feed a suitable DLL.
    Note: Alternatively, you can use an external pin to feed into the DLL input reference clock. The available pins are also listed in the External Memory Interfaces chapter of the relevant device family handbook. You can also activate an unused PLL clock output, set it at the desired DLL frequency, and route it to a PLL dedicated output pin. Connect a trace on the PCB from this output pin to the DLL reference clock pin, but be sure to include any signal integrity requirements such as terminations.
  4. Read data pins require the usage of DQS and DQ group pins to have access to the DLL control signals.
    Note: In addition, QVLD pins in RLDRAM II and RLDRAM 3 DRAM, and QDR II+ SRAM must use DQS group pins, when the design uses the QVLD signal. None of the Intel® FPGA IP uses QVLD pins as part of read capture, so theoretically you do not need to connect the QVLD pins if you are using the Intel® solution. It is good to connect it anyway in case the Intel® solution gets updated to use QVLD pins.
  5. In differential clocking (DDR3/DDR2 SDRAM, RLDRAM II, and RLDRAM 3 interfaces), connect the positive leg of the read strobe or clock to a DQS pin, and the negative leg of the read strobe or clock to a DQSn pin. For QDR II or QDR II+ SRAM devices with 2.5 or 1.5 cycles of read latency, connect the CQ pin to a DQS pin, and the CQn pin to a CQn pin (and not the DQSn pin). For QDR II or QDR II+ SRAM devices with 2.0 cycles of read latency, connect the CQ pin to a CQn pin, and the CQn pin to a DQS pin.
  6. Write data (if unidirectional) and data mask pins (DM or BWSn) pins must use DQS groups. While the DLL phase shift is not used, using DQS groups for write data minimizes skew, and must use the SW and TCCS timing analysis methodology.
  7. Assign the write data strobe or write data clock (if unidirectional) in the corresponding DQS/DQSn pin with the write data groups that place in DQ pins (except in RLDRAM II and RLDRAM 3 CIO devices). Refer to the Pin-out Rule Exceptions for your memory interface protocol.
    Note: When interfacing with a DDR, or DDR2, or DDR3 SDRAM without leveling, put the CK and CK# pairs in a single ×4 DQS group to minimize skew between clocks and maximize margin for the tDQSS, tDSS, and tDSH specifications from the memory devices.
  8. Assign any address pins to any user I/O pin. To minimize skew within the address pin group, you should assign the address pins in the same bank or side of the device.
  9. Assign the command pins to any I/O pins and assign the pins in the same bank or device side as the other memory interface pins, especially address and memory clock pins. The memory device usually uses the same clock to register address and command signals.
    • In QDR II and QDR II+ SRAM interfaces where the memory clock also registers the write data, assign the address and command pins in the same I/O bank or same side as the write data pins, to minimize skew.
    • For more information about assigning memory clock pins for different device families and memory standards, refer to Pin Connection Guidelines Tables.

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