External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

5.3.2. Outputs from the FPGA to the RLDRAM II and RLDRAM 3 Components

The following output signals are from the FPGA to the RLDRAM II and RLDRAM 3 components:
  • Write data (DQ on the bidirectional data signals for CIO RLDRAM II and RLDRAM 3)
  • Data mask (DM)
  • Address, bank address
  • Command (CS, WE, and REF)
  • Clocks (CK/CK# and DK/DK#)

For point-to-point single-ended signals requiring external termination, Intel recommends that you place a fly-by termination by terminating at the end of the transmission line after the receiver to avoid unterminated stubs. The guideline is to place the fly-by termination within 100 ps propagation delay of the receiver.

Although not recommended, you can place the termination before the receiver, which leaves an unterminated stub. The stub delay is critical because the stub between the termination and the receiver is effectively unterminated, causing additional ringing and reflections. Stub delays should be less than 50 ps.

Intel recommends that the differential clocks, CK, CK# and DK, DK# (RLDRAM II) and CK, CK# (RLDRAM 3), use a differential termination at the end of the trace at the external memory component. Alternatively, you can terminate each clock output with a parallel termination to VTT.