External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.6. Report SDC

The Report SDC task in the Timing Analyzer generates the SDC assignment reports for your design. The Timing Analyzer generates this constraint report by sourcing the .sdc. The SDC assignment reports show the constraint applied in the design.

For example, the reports may include the following constraints:

  • Create Clock
  • Create Generated Clock
  • Set Clock Uncertainty
  • Set Input Delay
  • Set Output Delay
  • Set False Path
  • Set Multicycle Path
  • Set Maximum Delay
  • Set Minimum Delay

The following figure shows the SDC assignments generated by the Report SDC task for a DDR3 SDRAM core design. The Timing Analyzer uses these constraint numbers in analysis to calculate the timing margin. Refer to the .sdc files of each constraints number.

Figure 70. SDC Assignments Report Window