External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.1.19.1. Maximum Number of DDR SDRAM Interfaces Supported per FPGA

The following table describes the maximum number of ×8 DDR SDRAM components that can fit in the smallest and biggest devices and pin packages assuming the device is blank.

Each interface of size n, where n is a multiple of 8, consists of:

  • n DQ pins (including error correction coding (ECC))
  • n/8 DM pins
  • n/8 DQS pins
  • 18 address pins
  • 6 command pins (CAS#, RAS#, WE#, CKE, and CS#)
  • 1 CK, CK# pin pair for up to every three ×8 DDR SDRAM components
Table 5.  Maximum Number of DDR SDRAM Interfaces Supported per FPGA

Device

Device Type

Package Pin Count

Maximum Number of Interfaces

Arria II GX

EP2AGX190

EP2AGX260

1,152

Four ×8 interfaces or one ×72 interface on each side (no DQ pins on left side)

EP2AGX45

EP2AGX65

358

  • On top side, one ×16 interface
  • On bottom side, one ×16 interface
  • On right side (no DQ pins on left side), one ×8 interface

Arria II GZ

EP2AGZ300

EP2AGZ350

EP2AGZ225

1,517

Four ×8 interfaces or one ×72 interface on each side

EP2AGZ300

EP2AGZ350

780

  • On top side, three ×8 interfaces or one ×64 interface
  • On bottom side, three ×8 interfaces or one ×64 interface
  • No DQ pins on the left and right sides

Stratix III

EP3SL340

1,760

  • Two ×72 interfaces on both top and bottom sides
  • One ×72 interface on both right and left sides

EP3SE50

484

  • Two ×8 interfaces on both top and bottom sides
  • Three ×8 interface on both right and left sides

Stratix IV

EP4SGX290

EP4SGX360

EP4SGX530

1,932

  • One ×72 interface on each side

or

  • One ×72 interface on each side and two additional ×72 wraparound interfaces, only if sharing DLL and PLL resources

EP4SE530

EP4SE820

1,760

EP4SGX70

EP4SGX110

EP4SGX180

EP4SGX230

780

  • Three ×8 interfaces or one ×64 interface on both top and bottom sides
  • On left side, one ×48 interface or two ×8 interfaces
  • No DQ pins on the right side

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