External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents Board Effects

Unequal length PCB traces result in delays reducing timing margins. Skews between different memory ranks can further reduce the timing margins in multiple chip select topologies.

Board skews can also affect the extent to which the FPGA can calibrate to the different ranks. If the skew between various signals for different ranks is large enough, the timing margin on the fully calibrated paths such as write leveling and resynchronization changes.

To account for all these board effects for Arria II GX, Arria II GZ, Arria V, Cyclone V, Stratix IV, and Stratix V devices, refer to the Board Settings page in the UniPHY-based controller parameter editors.

Note: To perform multiple chip select timing deration for other Intel devices (for example, Stratix III devices), use the Excel-based calculator available from www.altera.com.

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