External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents OCT and ODT Usage

Modern external memory interface designs typically use OCT for the FPGA end of the line, and ODT for the memory component end of the line. If either the OCT or ODT are incorrectly configured or enabled, signal integrity problems occur.

If the design uses OCT, RUP or RDN pins must be placed correctly for the OCT to work. If you do not place these pins, the Intel® Quartus® Prime software allocates them automatically with the following warning:

Warning: No exact pin location assignment(s) for 2 pins of 110 total pins
Info: Pin termination_blk0~_rup_pad not assigned to an exact location on the device
Info: Pin termination_blk0~_rdn_pad not assigned to an exact location on the device 

If you see these warnings, the RUP and RDN pins may have been allocated to a pin that does not have the required external resistor present on the board. This allocation renders the OCT circuit faulty, resulting in unreliable calibration and or interface behavior. The pins with the required external resistor must be specified in the Intel® Quartus® Prime software.

For the FPGA, ensure that you perform the following:

  • Specify the RUP and RDN pins in either the projects HDL port list, or in the assignment editor (termination_blk0~_rup_pad/ termination_blk0~_rdn_pad).
  • Connect the RUP and RDN pins to the correct resistors and pull-up and pull-down voltage in the schematic or PCB.
  • Contain the RUP and RDN pins within a bank of the device that is operating at the same VCCIO voltage as the interface that is terminated.
  • Check that only the expected number of RUP and RDN pins exists in the project pin-out file. Look for Info: Created on-chip termination messages at the fitter stage for any calibration blocks not expected in your design.
  • Review the Fitter Pin-Out file for RUP and RDN pins to ensure that they are on the correct pins, and that only the correct number of calibration blocks exists in your design.
  • Check in the fitter report that the input, output, and bidirectional signals with calibrated OCT all have the termination control block applicable to the associated RUP and RDN pins.

For the memory components, ensure that you perform the following:

  • Connect the required resistor to the correct pin on each and every component, and ensure that it is pulled to the correct voltage.
  • Place the required resistor close to the memory component.
  • Correctly configure the IP to enable the desired termination at initialization time.
  • Check that the speed grade of memory component supports the selected ODT setting.
  • Check that the second source part that may have been fitted to the PCB, supports the same ODT settings as the original