External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.13.2. Timing Deration using the Board Settings

When you target Arria II GX, Arria II GZ, Arria V, Cyclone V, Stratix IV, or Stratix V devices, the UniPHY-based parameter editors include the Board Settings page, to automatically account for the timing deration caused by the multiple chip selects in your design.

When you target Stratix III devices, you can derate single chip-select designs using the parameter editors to account for the skews, ISI, and slew rates in the Board Settings page.

If you are targeting Stratix III devices you see the following warning:

"Warning: Calibration performed on all chip selects, timing analysis only performed on first chip select. Manual timing derating is required"

Note: You must perform manual timing deration using the Excel-based calculator.

The Board Settings page allows you to enter the parameters related to the board design including skews, signal integrity, and slew rates. The Board Settings page also includes the board skew setting parameter, Addr/Command to CK skew.

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