External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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2.8. Document Revision History

Date Version Changes
March 2023 2023.03.06
  • Removed all Intel® Arria® 10 and Intel® Stratix® 10-related content.
May 2017 2017.05.08
  • Added Channel Signal Integrity Measurement section.
  • Added Stratix 10 to several sections.
  • Removed QDR-IV future support note from Package Deskew Recommendations for Arria 10 and Stratix 10 Devices section.
  • Rebranded as Intel.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02
  • Minor change to Clock Routing description in the DDR2 SDRAM Layout Guidelines table in Layout Guidelines for DDR2 SDRAM Interface.
  • Added maximum length of the first SDRAM to the last SDRAM for clock routing and address and command routing for DDR4, in Layout Guidelines for DDR3 and DDR4 SDRAM Interfaces.
  • Removed DRAM Termination Guidance from Layout Guidelines for DDR3 and DDR4 SDRAM Interfaces.
  • Added DDR4 support to Length Matching Rules.
November 2015 2015.11.02
  • Minor additions to procedure steps in DQ/DQS/DM Deskew and Address and Command Deskew.
  • Added reference to Micron Technical Note in Layout Guidelines for DDR3 and DDR4 SDRAM Interfaces.
  • Changed title of Board Termination for DDR2 SDRAM to Termination for DDR2 SDRAM and Board Termination for DDR3 SDRAM to Termination for DDR3 SDRAM.
  • Changed title of Leveling and Dynamic ODT to Leveling and Dynamic Termination.
  • Added DDR4 support in Dynamic ODT.
  • Removed topics pertaining to older device families.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15
  • Added MAX 10 to On-Chip Termination topic.
  • Added MAX 10 to Termination Recommendations table in Recommended Termination Schemes topic.

August 2014 2014.08.15
  • Added Arria V Soc and Cyclone V SoC devices to note in Leveling and Dynamic ODT section.
  • Added DDR4 to Read and Write Leveling section.
  • Revised text in On-Chip Termination section.
  • Added text to note in Board Termination for DDR3 SDRAM section.
  • Added Layout Approach information in the DDR3 and DDR4 on Arria 10 Devices section.
  • Recast expressions of length-matching measurements throughout DDR2 SDRAM Layout Guidelines table.
  • Made several changes to DDR3 and DDR4 SDRAM Layout Guidelines table:
    • Added Spacing Guidelines section.
    • Removed millimeter approximations from lengths expressed in picoseconds.
    • Revised Guidelines for Clock Routing, Address and Command Routing, and DQ, DM, and DQS Routing Rules sections.
  • Added Spacing Guidelines information to Design Layout Guidelines section.
December 2013 2013.12.16
  • Review and minor updates of content.
  • Consolidated General Layout Guidelines.
  • Added DDR3 and DDR4 information for Arria 10 devices.
  • Updated chapter title to include DDR4 support.
  • Removed references to ALTMEMPHY.
  • Removed references to Cyclone III and Cyclone IV devices.
  • Removed references to Stratix II devices.
  • Corrected Vtt to Vdd in Memory Clocks for DDR3 SDRAM UDIMM section.
November 2012 5.0
  • Updated Layout Guidelines for DDR2 SDRAM Interface and Layout Guidelines for DDR3 SDRAM Interface.

  • Added LRDIMM support.
  • Added Package Deskew section.
June 2012 4.1 Added Feedback icon.
November 2011 4.0 Added Arria V and Cyclone V information.
June 2011 3.0
  • Merged DDR2 and DDR3 chapters to DDR2 and DDR3 SDRAM Interface Termination and Layout Guidelines and updated with leveling information.

  • Added Stratix V information.
December 2010 2.1

Added DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines chapter with Stratix V information.

July 2010 2.0 Updated Arria II GX information.
April 2010 1.0 Initial release.