External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.1.3. Internal FPGA Timing Paths

Other timing paths that have an impact on memory interface timing include FPGA internal fMAX paths for PHY and controller logic.

This timing analysis is common to all FPGA designs. With appropriate timing constraints on the design (such as clock settings), the Timing Analyzer reports the corresponding timing margins.

For more information about the Timing Analyzer, refer to the Intel Quartus Prime Timing Analyzer chapter in volume 3 of the Quartus Prime Standard Edition Handbook.