9.1.3. Internal FPGA Timing Paths
This timing analysis is common to all FPGA designs. With appropriate timing constraints on the design (such as clock settings), the TimeQuest Timing Analyzer reports the corresponding timing margins.
For more information about the TimeQuest Timing Analyzer, refer to the Quartus Prime TimeQuest Timing Analyzer chapter in volume 3 of the Quartus Prime Handbook.
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