External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback

2.6. Design Layout Guidelines

The general layout guidelines in this topic apply to DDR3 SDRAM interfaces.

These guidelines will help you plan your board layout, but are not meant as strict rules that you must adhere to. Intel recommends that you perform your own board-level simulations to ensure that the layout you choose for your board allows you to achieve your desired performance.

For more information about how the memory manufacturers route these address and control signals on their DIMMs, refer to the Cadence PCB browser from the Cadence website, at www.cadence.com. The various JEDEC* example DIMM layouts are available from the JEDEC* website, at www.jedec.org.

For assistance in calculating board skew parameters, refer to the board skew calculator tool, which is available at the Intel website.

  1. The following layout guidelines include several +/- length based rules. These length based guidelines are for first order timing approximations if you cannot simulate the actual delay characteristic of the interface. They do not include any margin for crosstalk.
  2. To ensure reliable timing closure to and from the periphery of the device, signals to and from the periphery should be registered before any further logic is connected.

Intel recommends that you get accurate time base skew numbers for your design when you simulate the specific implementation.