External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

8.2.7. PHY-Only Simulation

To enable PHY-only simulation in the parameter editor, under PHY Settings tab, in the FPGA section, turn on Generate PHY only. This setting also applies to designs using Qsys. This option allows you to replace the Intel high-performance memory controllers with your own custom controller.

When you are using a standard UniPHY memory interface, by default, the parameter editor generates an external memory interface with a controller and a PHY. The controller and PHY are connected internally with the Altera PHY interface (AFI). The memory interface has an Avalon slave port that connects to the controller to allow communication from the user logic. When you turn on the PHY-only option, the parameter editor generates the PHY without the controller. In this case, the PHY is accessed via the AFI port, which can be externally connected to a custom controller. In the example design, a controller is instantiated externally to the memory interface. This provides a fully functional example design and demonstrates how to connect the controller to manage the transactions from the traffic generator.

The following figure shows the difference in the UniPHY memory interface when the PHY-only option is enabled.

Figure 65. PHY-only Option


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