13.1. Performing Vector-Based Power Analysis with the Power Analyzer
To perform vector-based power analysis with the Power Analyzer using zero-delay simulation, follow these steps:
- Compile your design in the Quartus Prime software to generate a Netlist <project_name>. vo file for your design.
Note: The <project_name>.vo is generated in the last stage of a compile EDA Netlist Writer.
- Open the <project_name>.vo file in a text editor.
- In the <project_name>.vo file, locate the include statement for <project_name>.sdo, and comment-out that include statement. Save the <project_name>.vo file.
- Create a simulation script containing device model files and libraries and design specific files:
- Netlist file for the design, <project_name>.vo
- RTL or netlist file for the memory device
- Testbench RTL file
- Compile all the files.
- Invoke the simulator with commands to generate . vcd files.
- Generate .vcd files for the parts of the design that contribute the most to power dissipation.
- Run simulation.
- Use the generated .vcd files in the Power Analyzer as the signal activity input file.
- Run the Power Analyzer.
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