External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

13.1. Performing Vector-Based Power Analysis with the Power Analyzer

To perform vector-based power analysis with the Power Analyzer using zero-delay simulation, follow these steps:

  1. Compile your design in the Quartus Prime software to generate a Netlist <project_name>. vo file for your design.
    Note: The <project_name>.vo is generated in the last stage of a compile EDA Netlist Writer.
  2. Open the <project_name>.vo file in a text editor.
  3. In the <project_name>.vo file, locate the include statement for <project_name>.sdo, and comment-out that include statement. Save the <project_name>.vo file.
  4. Create a simulation script containing device model files and libraries and design specific files:
    • Netlist file for the design, <project_name>.vo
    • RTL or netlist file for the memory device
    • Testbench RTL file
  5. Compile all the files.
  6. Invoke the simulator with commands to generate . vcd files.
  7. Generate .vcd files for the parts of the design that contribute the most to power dissipation.
  8. Run simulation.
  9. Use the generated .vcd files in the Power Analyzer as the signal activity input file.
  10. Run the Power Analyzer.
Note: For more information about estimating power, refer to the Power Estimation and Analysis section in the Quartus Prime Handbook.

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