External Memory Interface Handbook Volume 2: Design Guidelines

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Date 5/08/2017
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7.3.4.3.3. Board Skew parameters for RLDRAM II and RLDRAM 3

The following table lists board skew parameters for RLDRAM II and RLDRAM 3 interfaces.
Table 81.  Parameter Descriptions

Parameter

Description

Maximum CK delay to device

The delay of the longest CK trace from the FPGA to any device/DIMM is expressed by the following equation:



where n is the number of memory clocks. For example, the maximum CK delay for two pairs of memory clocks is expressed by the following equation:



Maximum DK delay to device

The delay of the longest DK trace from the FPGA to any device/DIMM is expressed by the following equation:



where n is the number of DK. For example, the maximum DK delay for two DK is expressed by the following equation:



Minimum delay difference between CK and DK

The minimum delay difference between the CK signal and any DK signal when arriving at the memory device(s). The value is equal to the minimum delay of the CK signal minus the maximum delay of the DK signal. The value can be positive or negative.

The minimum delay difference between CK and DK is expressed by the following equations:



where n is the number of memory clocks and m is the number of DK. For example, the minimum delay difference between CK and DK for two pairs of memory clocks and four DK signals (two DK signals for each clock) is expressed by the following equation:



Maximum delay difference between CK and DK

The maximum delay difference between the CK signal and any DK signal when arriving at the memory device(s). The value is equal to the maximum delay of the CK signal minus the minimum delay of the DK signal. The value can be positive or negative.

The maximum delay difference between CK and DK is expressed by the following equations:



where n is the number of memory clocks and m is the number of DK. For example, the maximum delay difference between CK and DK for two pairs of memory clocks and four DK signals (two DK signals for each clock) is expressed by the following equation:



Maximum delay difference between devices

The maximum delay difference of data signals between devices is expressed by the following equation:



For example, in a two-device configuration there is greater propagation delay for data signals going to and returning from the furthest device relative to the nearest device. This parameter is applicable for depth expansion. Set the value to 0 for non-depth expansion design.

Maximum skew within QK group

The maximum skew between the DQ signals referenced by a common QK signal.

Maximum skew between QK groups

The maximum skew between QK signals of different data groups.

Maximum skew within address/command bus

The maximum skew between the address/command signals.



Average delay difference between address/command and CK

A value equal to the average of the longest and smallest address/command signal delay values, minus the delay of the CK signal. The value can be positive or negative.

The average delay difference between the address and command and CK is expressed by the following equation:



where n is the number of memory clocks.

Average delay difference between write data signals and DK

A value equal to the average of the longest and smallest write data signal delay values, minus the delay of the DK signal. Write data signals include the DQ and DM signals. The value can be positive or negative.

The average delay difference between DQ and DK is expressed by the following equation:



where n is the number of DK groups.

Average delay difference between read data signals and QK

A value equal to the average of the longest and smallest read data signal delay values, minus the delay of the QK signal. The value can be positive or negative.

The average delay difference between DQ and QK is expressed by the following equation:



where n is the number of QK groups.

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