External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.5. Using PLL Guidelines

When using PLL for external memory interfaces, you must consider the following guidelines:
  • For the clock source, use the clock input pin specifically dedicated to the PLL that you want to use with your external memory interface. The input and output pins are only fully compensated when you use the dedicated PLL clock input pin. If the clock source for the PLL is not a dedicated clock input pin for the dedicated PLL, you would need an additional clock network to connect the clock source to the PLL block. Using additional clock network may increase clock jitter and degrade the timing margin.
  • Pick a PLL and PLL input clock pin that are located on the same side of the device as the memory interface pins.
  • Share the DLL and PLL static clocks for multiple memory interfaces provided the controllers are on the same or adjacent side of the device and run at the same memory clock frequency.
  • If your design uses a dedicated PLL to only generate a DLL input reference clock, you must set the PLL mode to No Compensation in the Quartus Prime software to minimize the jitter, or the software forces this setting automatically. The PLL does not generate other output, so it does not need to compensate for any clock path.
  • If your design cascades PLL, the source (upstream) PLL must have a low‑bandwidth setting, while the destination (downstream) PLL must have a high‑bandwidth setting to minimize jitter. Intel® does not recommend using cascaded PLLs for external memory interfaces because your design gets accumulated jitters. The memory output clock may violate the memory device jitter specification.
  • Use cascading PLLs at your own risk. For more information, refer to “PLL Cascading”.
  • If you are using Arria II GX devices, for a single memory instance that spans two right-side quadrants, use a middle-side PLL as the source for that interface.
  • If you are using Arria II GZ, Arria V GZ, Stratix III, Stratix IV, or Stratix V devices, for a single memory instance that spans two top or bottom quadrants, use a middle top or bottom PLL as the source for that interface. The ten dual regional clocks that the single interface requires must not block the design using the adjacent PLL (if available) for a second interface.

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