External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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1.2.6.4. Clock Network Usage in UniPHY-based Memory Interfaces—DDR2 and DDR3 SDRAM (1) (2)

The following table lists clock network usage in UniPHY-based memory interfaces for DDR2 and DDR3 protocols.
Table 20.  Clock Network Usage in UniPHY-based Memory Interfaces—DDR2 and DDR3 SDRAM

Device

DDR3 SDRAM

DDR2 SDRAM

Half-Rate

Half-Rate

Number of full-rate clock

Number of half-rate clock

Number of full-rate clock

Number of half-rate clock

Stratix III

3 global

1 global

1 regional

1 global

2 global

1 global

1 regional

Arria II GZ and Stratix IV

3 global

1 global

1 regional

1 regional

2 regional

1 global

1 regional

Arria V GZ and Stratix V

1 global

2 regional

2 global

1 regional

2 regional

2 global

Notes to Table:

  1. There are two additional regional clocks, pll_avl_clk and pll_config_clk for DDR2 and DDR3 SDRAM with UniPHY memory interfaces.
  2. In multiple interface designs with other IP, the clock network might need to be modified to get a design to fit. For more information, refer to the Clock Networks and PLLs chapter in the respective device handbooks.