External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

4.1.4. LPDDR2 Layout Guidelines

The following table lists the LPDDR2 SDRAM general routing layout guidelines.
Note: The following layout guidelines include several +/- length-based rules. These length‑based guidelines are for first order timing approximations if you cannot simulate the actual delay characteristics of your PCB implementation. They do not include any margin for crosstalk. Intel recommends that you get accurate time base skew numbers when you simulate your specific implementation.
Table 41.  LPDD2 Layout Guidelines

Parameter

Guidelines

General Routing

  • If you must route signals of the same net group on different layers with the same impedance characteristic, simulate your worst case PCB trace tolerances to ascertain actual propagation delay differences. Typical layer to layer trace delay variations are of 15 ps/inch order.
  • Avoid T-junctions greater than 75 ps (approximately 25 mils, 6.35 mm).
  • Match all signals within a given DQ group with a maximum skew of ±10 ps and route on the same layer.

Clock Routing

  • Route clocks on inner layers with outer-layer run lengths held to under 150 ps.
  • These signals should maintain a 10-mil (0.254 mm) spacing from other nets.
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Differential clocks should maintain a length-matching between P and N signals of ±2 ps.
  • Space between different clock pairs should be at least three times the space between the traces of a differential pair.

Address and Command Routing

  • To minimize crosstalk, route address, and command signals on a different layer than the data and data mask signals.
  • Do not route the differential clock (CK/CK#) and clock enable (CKE) signals close to the address signals.

External Memory Routing Rules

  • Apply the following parallelism rules for the LPDDR2 SDRAM data groups:
    • 4 mils for parallel runs < 0.1 inch (approximately 1× spacing relative to plane distance).
    • 5 mils for parallel runs < 0.5 inch (approximately 1× spacing relative to plane distance).
    • 10 mils for parallel runs between 0.5 and 1.0 inches (approximately 2× spacing relative to plane distance).
    • 15 mils for parallel runs between 1.0 and 2.8 inch (approximately 3× spacing relative to plane distance).
  • Apply the following parallelism rules for the address/command group and clocks group:
    • 4 mils for parallel runs < 0.1 inch (approximately 1× spacing relative to plane distance)
    • 10 mils for parallel runs < 0.5 inch (approximately 2× spacing relative to plane distance)
    • 15 mils for parallel runs between 0.5 and 1.0 inches (approximately 3× spacing relative to plane distance)
    • 20 mils for parallel runs between 1.0 and 2.8 inches (approximately 4× spacing relative to plane distance)

Maximum Trace Length

  • Keep traces as short as possible. The maximum trace length of all signals from the FPGA to the LPDDR2 SDRAM components should be less than 509 ps. Intel recommends that you simulate your design to ensure good signal integrity.

Trace Matching Guidance

The following layout approach is recommended, based on the preceding guidelines:

  1. Route the differential clocks (CK/CK#) and data strobe (DQS/DQS#) with a length-matching between P and N signals of ±2 ps.
  2. Route the DQS /DQS# associated with a DQ group on the same PCB layer. Match these DQS pairs to within ±5 ps.
  3. Set the DQS/DQS# as the target trace propagation delay for the associated data and data mask signals.
  4. Route the data and data mask signals for the DQ group ideally on the same layer as the associated DQS/DQS# to within ±10 ps skew of the target DQS/DQS#.
  5. Route the CK/CK# clocks and set as the target trace propagation delays for the DQ group. Match the CK/CK# clock to within ±50 ps of all the DQS/DQS#.
  6. Route the address/control signal group (address, CS, CKE) ideally on the same layer as the CK/CK# clocks, to within ±20 ps skew of the CK/CK# traces.

This layout approach provides a good starting point for a design requirement of the highest clock frequency supported for the LPDDR2 SDRAM interface.

Note: You should create your project in the Quartus® Prime software with a fully implemented LPDDR2 interface, and observe the interface timing margins to determine the actual margins for your design.

Although the recommendations in this chapter are based on simulations, you can apply the same general principles when determining the best termination scheme, drive strength setting, and loading style to any board design. Even armed with this knowledge, it is still critical that you simulate your design with IBIS or HSPICE models, to determine the quality of signal integrity in your design.

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