9.3. Timing Constraint and Report Files for UniPHY IP
One set of files are used for the synthesis project, which is available under the <variation_name> folder located in the main project folder while the other set of files are the example designs, located in the <variation_name>example design\example_project folder.
The project folders contain the following files for timing constraints and reporting scripts:
The <variation_name>.sdc is listed in the wizard-generated Quartus Prime IP File (.qip). Including this file in the project allows the Quartus Prime Synthesis and Fitter to use the timing driven compilation to optimize the timing margins.
To analyze the timing margins for all UniPHY timing paths, execute the Report DDR function in the Timing Analyzer.
The UniPHY IP uses the .sdc to constrain internal FPGA timing paths, address and command paths, and clock-to-strobe timing paths, and more specifically:
- Creating clocks on PLL inputs
- Creating generated clocks
- Calling derive_clock_uncertainty
- Cutting timing paths for specific reset paths
- Setting input and output delays on DQ inputs and outputs
- Setting output delays on address and command outputs (versus CK/CK# outputs)
This script includes the memory, FPGA, and board timing parameters for your variation. It is included within <variation_name>_report_timing.tcl and <variation_name>.sdc.
This script reports the timing slack for your variation. It runs automatically during compilation (during static timing analysis). You can also run this script with the Report DDR task in the Timing Analyzer. This script is run for every instance of the same variation.
This script contains high-level procedures that the <variation_name>_report_timing.tcl script uses to compute the timing slack for your variation. This script runs automatically during compilation.
This script is a library of functions and procedures that the <variation_name>_report_timing.tcl and <variation_name> .sdc scripts use. The <variation_name>_pin_assignments.tcl script, which is not relevant to timing constraints, also uses this library.
This script defines some of the parameters that describe the geometry of the core and the PLL configuration. Do not change this file, except when you modify the PLL through the parameter editor. In this case, the changes to the PLL parameters do not automatically propagate to this file and you must manually apply those changes in this file.