External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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11.1.1. Interface Standard

Complying with certain interface standard specifications affects controller efficiency.

When interfacing the memory with the DDR2 or DDR3 SDRAM controllers, you must follow certain timing specifications and perform the following bank management operations:

  • Activate

    Before you issue any read (RD) or write (WR) commands to a bank within a DDR2 SDRAM device, you must open a row in that bank using the activate (ACT) command. After you open a row, you can issue a read or write command to that row based on the tRCD specification. Reading or writing to a closed row has negative impact on the efficiency as the controller has to first activate that row and then wait until tRCD time to perform a read or write.

  • Precharge

    To open a different row in the same bank, you must issue a precharge (PCH) command. The precharge command deactivates the open row in a particular bank or the open row in all banks. Switching a row has a negative impact on the efficiency as you must first precharge the open row, then activate the next row and wait tRCD time to perform any read or write operation to the row.

  • Device CAS latency

    The higher the CAS latency, the less efficient an individual access. The memory device has its own read latency, which is about 12 ns to 20 ns regardless of the actual frequency of the operation. The higher the operating frequency, the longer the CAS latency is in number of cycles.

  • Refresh

    A refresh, in terms of cycles, consists of the precharge command and the waiting period for the auto refresh. Based on the memory data sheet, these components require the following values:

    • tRP = 12 ns, 3 clock cycles for a 200-MHz operation (5 ns period for 200 MHz)
    • tRFC = 75 ns, 15 clock cycles for a 200-MHz operation.

    Based on this calculation, a refresh pauses read or write operations for 18 clock cycles. So, at 200 MHz, you lose 1.15% (18 x 5 ns/7.8 us) of the total efficiency.