External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback

10.1.5. Planning Your Design

It is important to understand your design and to plan its resource usage and layout. Include the following steps in your design planning:
  1. Plan the total number of DQS groups and total number of other pins required in your shared area. Use the Pin Planner to assist with this activity.
  2. Decide which PLLs or clock networks can be shared between IP blocks, then ensure that sufficient resources are available. For example, if an IP core requires a regional clock network, a PLL located on the opposite side of the device cannot be used.
  3. Calculate the number of total clock networks and types required when trying to combine multiple instances of IP.
  4. You must understand the number of quadrants that the IP uses and if this number can be reduced. For example, an interface may be autoplaced across an entire side of the device, but may be constrained to fit in a single bank.

By optimizing physical placement, you ensure that the system uses regional clock networks wherever possible. The use of regional clock networks instead of dual-regional clock networks can help maintain clock net resources and simplify routing.