External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

9.12. Optimizing Timing

For full-rate designs you may need to use some of the Quartus Prime advanced features, to meet core timing, by following these steps:
  1. On the Assignments menu click Settings. In the Category list, click Analysis & Synthesis Settings. For Optimization Technique select Speed.
Figure 93. Optimization Technique

  • Turn on Perform physical synthesis for combinational logic.

    For more information about physical synthesis, refer to the Netlist and Optimizations and Physical Synthesis chapter in the Quartus Prime Software Handbook.

  • Turn on Perform register retiming
  • Turn on Perform automatic asynchronous signal pipelining
  • Turn on Perform register duplication
  • You can initially select Normal for Effort level, then if the core timing is still not met, select Extra.
Figure 94. Physical Synthesis Optimizations

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