External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.11.2. Incomplete Timing Margin Report

The timing report may not include margin information for certain timing paths if certain memory interface pins are optimized away during synthesis.

Verify that all memory interface pins appear in the <variation>_all_pins.txt file generated during compilation, and ensure that they connect to the I/O pins of the top‑level FPGA design.

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